1. Field of the Invention
The present invention relates to circuitry for controlling voltage as a function of time. In particular, the present invention relates to circuitry for regulating the voltage available at a certain point in time. This includes, but is not limited to, reducing noise (overshoot and undershoot) associated with the switching of electrical signals transmitted from one location to another. The present invention is a wave shaping circuit particularly useful with Complementary Metal Oxide Semiconductor (CMOS) circuits.
2. Description of the Prior Art
Electrical signal transmission circuits such as output buffers are used to transfer electrical signals of desired amplitude and strength. Signal transfers occur by way of interfaces, such as buses, that couple active devices that are either on the same semiconductor-based system or on different systems. The systems may be located proximate to one another, or they may be some distance from one another. One example of a proximate system interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote system interface requiring one or more bus connections is the coupling of one computing system to another, such as through a telephone transmission line that is, effectively, a voice/data bus. More generally, any system used to transfer electrical signals from one point to another, whether digital or analog, requires some arrangement for ensuring that the transfer occurs as smoothly as possible when desired.
As indicated, signal transmission circuits are used to ensure that electrical signals are transferred as accurately and as quickly as possible. It is often the case, however, that when transmission rates increase, signal accuracy suffers. In particular, it is well known that rapid signal transmission may be accompanied by signal bounce. That is, the noise or ringing associated with the undershoot and overshoot of a final steady state logic HIGH or logic LOW signal that occurs in the transition between those two logic levels. The difference in the potentials associated with a HIGH signal and a LOW signal may be as small as 0.4V or as great as 5V. For CMOS-based logic, for example, a logic HIGH corresponds to a nominal 5.0V potential (for a 5.0V power supply) and a nominal 3.3V potential (for a 3.3V power supply), while a logic LOW is essentially equivalent to ground (GND) or 0.0V.
The potentials associated with HIGH and LOW signals described above are idealized values. In fact, HIGHS and LOWS generally fall within a range of potentials associated with the indicated values. Thus, for a 3.3V supply, a HIGH signal may be supplied at 2.6V, for example, while a LOW signal may actually be associated with a 0.7V value. As the potentials of the power supplies used to power circuitry move closer to GND, the signal bounce mentioned above takes on greater importance. In particular, the initial oscillation around the ultimate steady state value that occurs when the transition between HIGH and LOW is triggered may vary enough to generate a false logic signal. The noise swing may be enough to cause a LOW signal to transition to a HIGH signal potential and vice-versa, or it may be variable enough that the signal is not clearly at either a HIGH or a LOW. Either situation is undesirable. For that reason, it is becoming increasingly important that the transitions between HIGH and LOW occur with less noise than has been previously experienced.
Clearly, unexpected changes in logic values are not desirable. This problem is more likely to occur as transmission rates are increased. Increasing transmission rates enables the transfer of more data in a shorter time period and so is desirable in many respects. However, the gain in increased transmission rate is often undermined by an increase in signal noise. That is, a rapid change in signal level creates an oscillation about the steady state value corresponding to the sudden switching on or off of a transistor. Variations in the loads coupled to the outputs of such circuits also affect noise characteristics. As transistors become increasingly smaller in order to achieve the faster transmission rates of interest, the signal bounce that occurs with the rapid switching often creates reflections in transmission media, such as telephone transmission lines where reflections will cause signal errors. It is therefore important to enable "gentle" switching of transmission circuits so that signal noise is reduced.
Moreover, in order to improve the compatibility of disparate computing systems, it is of importance to be able to regulate the rate at which signal transitions occur. In that regard, it would be of value to be able to control the rate at which a signal transition occurs. While this control may be regulated to a certain extent using delay stages, such as by employing chains of inverters, there remains uncertainty in the application of such arrangements in that the delay associated with such stages may vary unacceptably. Additionally, as computing systems become increasingly sophisticated, it is desirable to enable the designer to tailor the signal transition rate.
A simplified illustration of a prior-art CMOS-based signal transmission (buffer) circuit of the type that exhibits unacceptable signal bounce characteristics is presented in FIG. 1. The buffer circuit includes an input node input for receiving an electrical signal that triggers operation of the buffer, and an output node output for the transfer of that signal to downstream circuitry. The input node is coupled to an inverter IV1 formed of P-type MOS transistor M1 and N-type MOS transistor M2. The output of the inverter IV1 is connected to the control node of a second inverter IV2 formed of pull-up P-type MOS transistor M3 and pull-down N-type MOS transistor M4. Those skilled in the art will recognize that additional inverters can be used between inverters IV1 and IV2 as delay stages.
As in any CMOS logic circuit, one and only one of transistors M3 and M4 is supposed to be turned on at a given time. When transistor M3 is on, the gate-source voltage (Vgs) exceeds the transistor's threshold voltage (Vt). The output node is at a logic high potential equivalent to high-potential power rail Vcc less the drain-source voltage (Vds) drop associated with transistor M3. When transistor M4 is on, the output node is at a logic low potential equivalent to low-potential power rail GND. It can be seen that signal bounce at the control nodes of transistors M3 and M4 may create the situation where the wrong one may be on, they may be conducting simultaneously, or they may both be off. As indicated, in most instances, neither situation is desirable. Further, the prior art buffer of FIG. 1 offers little control over the signal transmission rate from input to output.
Therefore, what is needed is a signal transmission circuit that reduces the noise associated with signal switching. What is also needed is a signal transmission circuit that may be used to tailor the shape of the signal passing between the input and output nodes of the circuit. Further, what is needed is such a wave shaping signal transmission circuit that achieves the noted goals without complicated circuitry that takes up valuable layout space. In general terms, what is needed is a signal transmission circuit that permits a system designer to control voltage as a function of time, whether to smooth the signal, to set the transmission rate, or for any other purpose of interest, digital or analog.